SAB-C167CR-LM

Product Summary

SAB-C167CR-LM The C167CR derivatives are high performance derivatives of the
Infineon C166Family of full featured single-chip CMOS microcontrollers. SAB-C167CR-LM
They combine high CPU performance (up to 16.5 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. SAB-C167CR-LM They also
provide clock generation via PLL and variouson-chip memory modules such as program
ROM, internal RAM, and extension RAM.

Parametrics

Derivative1) Program XRAM Size Operating Package
ROM Size Frequency
SAK-C167SR-LM – 2 Kbytes 25 MHz P-MQFP-144-8
SAB-C167SR-LM
SAK-C167SR-L33M – 2 Kbytes 33 MHz P-MQFP-144-8
SAB-C167SR-L33M
SAK-C167CR-LM – 2 Kbytes 25 MHz P-MQFP-144-8
SAF-C167CR-LM
SAB-C167CR-LM
SAK-C167CR-L33M – 2 Kbytes 33 MHz P-MQFP-144-8
SAB-C167CR-L33M
SAK-C167CR-4RM 32 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8
SAB-C167CR-4RM
SAK-C167CR-4R33M 32 Kbytes 2 Kbytes 33 MHz P-MQFP-144-8
SAB-C167CR-4R33M
SAK-C167CR-16RM 128 Kbytes 2 Kbytes 25 MHz P-MQFP-144-8
SAK-C167CR-16R33M 128 Kbytes 2 Kbytes 33 MHz P-MQFP-144-8
SAK-C167CR-LE – 2 Kbytes 25 MHz P-BGA-176-2

Features

1.High Performance 16-bit CPU with 4-Stage Pipeline
–80/60 ns Instruction Cycle Time at 25/33 MHz CPU Clock
–400/303 ns Multiplication (16 × 16 bits), 800/606 ns Division (32 / 16 bits)
–Enhanced Boolean Bit Manipulation Facilities
–Additional Instructions to Support HLL and Operating Systems
–Register-Based Design with Multiple Variable Register Banks
–Single-Cycle Context Switching Support
–16 Mbytes Total Linear Address Space for Code and Data
–1024 Bytes On-Chip Special Function Register Area
2.16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 40/30 ns
3.8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC)
4.Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5),
via prescaler or via direct clock input
5.On-Chip Memory Modules
–2 Kbytes On-Chip Internal RAM (IRAM)
–2 Kbytes On-Chip Extension RAM (XRAM)
–128/32 Kbytes On-Chip Mask ROM
6.On-Chip Peripheral Modules
–16-Channel 10-bit A/D Converter with Programmable Conversion Time
down to 7.8 μs
–Two 16-Channel Capture/Compare Units
–4-Channel PWM Unit
–Two Multi-Functional General Purpose Timer Units with 5 Timers
–Two Serial Channels (Synchronous/Asynchronous and
High-Speed-Synchronous)
–On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects
(Full CAN / Basic CAN)
7.Up to 16 Mbytes External Address Space for Code and Data
–Programmable External Bus Characteristics for Different Address Ranges
–Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit
Data Bus Width
–Five Programmable Chip-Select Signals
–Hold- and Hold-Acknowledge Bus Arbitration Support
8.Idle and Power Down Modes
9.Programmable Watchdog Timer and Oscillator Watchdog
10.Up to 111 General Purpose I/O Lines,
partly with Selectable Input Thresholds and Hysteresis
11.Supported by a Large Range of Development Tools like C-Compilers,
Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers,
Simulators, Logic Analyzer Disassemblers, Programming Boards
12.On-Chip Bootstrap Loader
13.144-Pin MQFP Package
14.176-Pin BGA Package1)

Diagrams