TMS320F2812PGF

Product Summary

The TMS320F2810 and TMS320F2812 devices, members of the TMS320C28x? DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in subsequent paragraphs.

Parametrics

FEATURE F2812
Instruction Cycle (at 150 MHz) 6.67 ns
Single-Access RAM (SARAM) (16-bit word) 18K
3.3-V On-Chip Flash (16-bit word) 128K
Code Security for On-Chip Flash/SARAM Yes
Boot ROM Yes
OTP ROM Yes
External Memory Interface Yes
Event Managers A and B (EVA and EVB) EVA, EVB
General-Purpose (GP) Timers 4
Compare (CMP)/PWM 18
Capture (CAP)/QEP Channels 6/2
Watchdog Timer Yes
12-Bit ADC Yes
Channels 18
32-bit CPU Timers 3
SPI Yes
SCIA, SCIB SCIA, SCIB
CAN Yes
McBSP Yes
Digital I/O Pins (Shared) 58
External Interrupts 3
Supply Voltage 1.8-V Core, 3.3-V I/O
Packaging 179-pin GHH
176-pin PGF
Product Status:
Product Preview (PP) PP
Advance Information (AI)
Production Data (PD)

Features

High-Performance Static CMOS Technology
– 150 MHz (6.67-ns Cycle Time)
– Low-Power (1.8-V Core, 3.3-V I/O) Design
– 3.3-V Flash Programming Voltage
High-Performance CPU (C28x)
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– 4M Linear Program Address Reach
– 4G Linear Data Address Reach
– Code-Efficient (in C/C++ and Assembly)
– TMS320F24x/LF240x Processor Source
Code Compatible
On-Chip Memory
– Up to 128K x 16 Flash
(8 x 4K and 6 x 16K Sectors)
– 2K x 16 OTP ROM
– L0 and L1: 2 Blocks of 4K x 16
Single-Access RAM (SARAM)
– H0: 1 Block of 8K x 16 SARAM
– M0 and M1: 2 Blocks of 1K x 16 SARAM
Boot ROM (4K x 16)
– With Software Boot Modes
– Standard Math Tables
External Interface (F2812)
– Up to 1.5M Total Memory
– Programmable Wait States
– Programmable Read/Write Strobe Timing
– Four Individual Chip Selects
Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
– Watchdog Timer Module
Three External Interrupts
Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
128-Bit Security Key/Lock
– Protects Flash/OTP and L0/L1 SARAM
– Prevents Firmware Reverse Engineering
Motor Control Peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240x Devices
Three 32-Bit CPU-Timers
Serial Port Peripherals
– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces
(SCIs), Standard UART
– Enhanced Controller Area Network
(eCAN)
– Multichannel Buffered Serial Port
(McBSP) With SPI Mode
12-Bit ADC, 16 Channels
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single Conversion Time: 200 ns
– Pipeline Conversion Time: 60 ns
Up to 56 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins
Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
Development Tools Include
– ANSI C/C++ Compiler/Assembler/Linker
– Supports TMS320C24x?/240x
Instructions
– Code Composer Studio? IDE
– DSP BIOS
– JTAG Scan Controllers?
(TI or Third-Party)
– Evaluation Modules
– Broad Third-Party Digital Motor Control
Support
Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
Package Options
– 179-Pin MicroStar BGA? With External
Interface (GHH) (F2812)
– 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Interface (PGF)
(F2812)
– 128-Pin LQFP Without External Interface
(PBK) (F2810)
Temperature Options:
– A:–40°C to 85°C
– S:–40°C to 125°C

Diagrams