TMS320C6711BGFN150

Product Summary

TMS320C6711BGFN150 The TMS320C67x? DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D
devices?) compose the floating-point DSP family in the TMS320C6000? DSP platform. The C6711, C6711B,
C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word
(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for
multichannel and multifunction applications.TMS320C6711BGFN150
The C6711/C6711B/C6711C/C6711D DSPs also have application-specific hardware logic, on-chip memory,
and additional on-chip peripherals.TMS320C6711BGFN150
The C6711/C6711B/C6711C/C6711D uses a two-level cache-based architecture and has a powerful and
diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level
1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a
512-Kbit memory space that is shared between program and data space. L2 memory can be configured as
mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The C6711/C6711B/C6711C/C6711D has a complete set of development tools which includes: a new C
compiler, an assembly optimizer to simplify programming and scheduling, and a Windows? debugger interface
for visibility into source code execution.

Parametrics

HARDWARE FEATURES INTERNAL CLOCK C6711/C6711B C6711C/C6711D
SOURCE (FLOATING-POINT DSPs) (FLOATING-POINT DSPs)
EMIF ECLKIN 1
SYSCLK3 or ECLKIN 1
EDMA CPU clock frequency 1 1
HPI CPU/2 clock frequency 1
McBSPs SYSCLK2 1
Peripherals 32Bit timers CPU/2 clock frequency 2
GPIO module SYSCLK2 2

Features

1.Excellent-Price/Performance Floating-Point
Digital Signal Processors (DSPs):
TMS320C67x? (C6711, C6711B, C6711C,
and C6711D)
? Eight 32-Bit Instructions/Cycle
? 100-,150-,167-,200-,250-MHz Clock Rates
? 10-, 6.7-, 6-, 5-, 4-ns Instruction Cycle
Time
? 600, 900, 1000, 1200, 1500 MFLOPS
2.Advanced Very Long Instruction Word
(VLIW) C67x? DSP Core
? Eight Highly Independent Functional
Units:
? Four ALUs (Floating- and Fixed-Point)
? Two ALUs (Fixed-Point)
? Two Multipliers (Floating- and
Fixed-Point)
? Load-Store Architecture With 32 32-Bit
General-Purpose Registers
? Instruction Packing Reduces Code Size
? All Instructions Conditional
3.Instruction Set Features
? Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
? Byte-Addressable (8-, 16-, 32-Bit Data)
? 8-Bit Overflow Protection
? Saturation
? Bit-Field Extract, Set, Clear
? Bit-Counting
? Normalization
4.L1/L2 Memory Architecture
? 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
? 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
? 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
5.Device Configuration
? Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
? Endianness: Little Endian, Big Endian
6.Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
6. 32-Bit External Memory Interface (EMIF)
? Glueless Interface to Asynchronous
Memories: SRAM and EPROM
? Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
? 256M-Byte Total Addressable External
Memory Space
7.16-Bit Host-Port Interface (HPI)
8.Two Multichannel Buffered Serial Ports
(McBSPs)
? Direct Interface to T1/E1, MVIP, SCSA
Framers
? ST-Bus-Switching Compatible
? Up to 256 Channels Each
? AC97-Compatible
? Serial-Peripheral-Interface (SPI)
Compatible (Motorola?)
9.Two 32-Bit General-Purpose Timers
10.Flexible Phase-Locked-Loop (PLL) Clock
Generator [C6711/11B]
11.Flexible Software Configurable PLL-Based
Clock Generator Module [C6711C/11D]
12.A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins [C6711C/11D]
13.IEEE-1149.1 (JTAG?)
Boundary-Scan-Compatible
14.256-Pin Ball Grid Array (BGA) Package
(GFN Suffix) [C6711/C6711B Only]
15.272-Pin Ball Grid Array (BGA) Package
(GDP Suffix) [C6711C/C6711D Only]
16.CMOS Technology
? 0.13-μm/6-Level Copper Metal Process
(C6711C/C6711D)
? 0.18-μm/5-Level Copper Metal Process
(C6711/11B)
17.3.3-V I/O, 1.4-V Internal (C6711D?250)
18.3.3-V I/O, 1.20-V Internal (C6711C/C6711D)?
19.3.3-V I/O, 1.8-V Internal (C6711B/C6711?100)
20.3.3-V I/O, 1.9-V Internal (C6711-150)

Diagrams