ATMEGA32L-8AU

Product Summary

ATMEGA32L-8AU:
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
ATMEGA32L-8AU:
The ATmega32 provides the following features: 32K bytes of In-System Programmable
Flash Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K
byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a
JTAG interface for Boundary-scan, On-chip Debugging support and programming, three
flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial
programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit
ADC with optional differential input stage with programmable gain (TQFP package only),
a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six
software selectable power saving modes.

Parametrics

鈥?2 Programmable I/O Lines;
鈥?0-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF;
Operating Voltages;
鈥?.7 - 5.5V for ATmega32L;
鈥?.5 - 5.5V for ATmega32;
Speed Grades;
鈥? - 8 MHz for ATmega32L;
鈥? - 16 MHz for ATmega32;
Power Consumption at 1 MHz, 3V, 25掳C for ATmega32L;
鈥揂ctive: 1.1 mA;
鈥揑dle Mode: 0.35 mA;
鈥揚ower-down Mode: < 1 ?A

Features

High-performance, Low-power AVR庐
8-bit Microcontroller
Advanced RISC Architecture
鈥?31 Powerful Instructions 鈥?Most Single-clock Cycle Execution
鈥?2 x 8 General Purpose Working Registers
鈥揊ully Static Operation
鈥揢p to 16 MIPS Throughput at 16 MHz
鈥揙n-chip 2-cycle Multiplier
Nonvolatile Program and Data Memories
鈥?2K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
鈥揙ptional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
鈥?024 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
鈥?K Byte Internal SRAM
鈥揚rogramming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
鈥揃oundary-scan Capabilities According to the JTAG Standard
鈥揈xtensive On-chip Debug Support
鈥揚rogramming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
鈥揟wo 8-bit Timer/Counters with Separate Prescalers and Compare Modes
鈥揙ne 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
鈥揜eal Time Counter with Separate Oscillator
鈥揊our PWM Channels
鈥?-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels in TQFP Package Only
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
鈥揃yte-oriented Two-wire Serial Interface
鈥揚rogrammable Serial USART
鈥揙n-chip Analog Comparator;
Special Microcontroller Features;
鈥揚ower-on Reset and Programmable Brown-out Detection;
鈥揑nternal Calibrated RC Oscillator;
鈥揈xternal and Internal Interrupt Sources;
鈥揝ix Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby;
I/O and Packages;
鈥?2 Programmable I/O Lines;
鈥?0-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF;
Operating Voltages;
鈥?.7 - 5.5V for ATmega32L;
鈥?.5 - 5.5V for ATmega32;
Speed Grades;
鈥? - 8 MHz for ATmega32L;
鈥? - 16 MHz for ATmega32;
Power Consumption at 1 MHz, 3V, 25掳C for ATmega32L;
鈥揂ctive: 1.1 mA;
鈥揑dle Mode: 0.35 mA;
鈥揚ower-down Mode: < 1 ?A

Diagrams

<IMG border=0 src="http://www.seekic.com/uploadfile/ic-mfg/20126293139871.jpg">